Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. Generally, these can be considered either volatile or non-volatile memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures. These architectures are named for the resemblance that the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuits, respectively.
In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (word lines) and their drains are connected to column bitlines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the wordline connected to their gates. The row of selected memory cells then place their stored data values on the column bitlines by flowing a differing current if in a programmed state or not programmed state from the connected source line to the connected column bitlines.
FIG. 1 shows a portion of a typical prior art NAND flash memory array. The selected word line 100 for the flash memory cells being programmed is typically biased by programming pulses that start at a voltage of around 16V and may incrementally increase to more than 20V. The selected word line 100 of the cells 101-103 to be programmed is biased at 19V. The unselected word lines for the remaining cells are biased at Vpass. This is typically in an approximate range of 9-10V. The bit lines of the cells 101-103 to be programmed are biased at 0V while the inhibited bit lines are biased at VCC.
As NAND flash memory is scaled, parasitic capacitance coupling between the selected word line and adjacent word lines becomes problematic. Because of the parasitic coupling, the neighboring cells are more prone to program disturb than the other cells that also share the common bit line with the cells being programmed. This causes the cells on neighboring wordlines to experience program disturb.
The program disturb condition has two operational types: boosting and Vpass. During boosting, the cell's channel is at a positive boosting voltage (e.g., 6V) with respect to the gate and the gate is at Vpgm (e.g., 19V). During Vpass, the cell's channel is at ground and the gate is at Vpass (e.g., 10V). In FIG. 1, the cells 120, 121 on the selected word line 100 and inhibited bit lines are influenced by boosting program disturb. The neighboring cells 110-118 that are coupled to the enabled bit lines experience Vpass program disturb.
FIG. 2 illustrates a cross-sectional view of a column of memory cells and the capacitive coupling resulting from a typical prior art programming operation. Each cell 200 is comprised of a floating gate 212 surrounded on either side by a tunnel dielectric 213 and a gate dielectric 211 that isolates the floating gate from the substrate 220 and the control gate 210, respectively. The column of cells is linked by source/drain regions 215, 216 that are formed in the substrate 220 between each cell stack 200.
During a typical prior art programming operation, the word line (WLn) of the cell to be programmed 200 is biased at Vpgm. The word lines of the unselected cells are biased at Vpass. The program disturb of cells coupled to WLn−1 and WLn+1 is going to be worse than other word lines due to the word line capacitive coupling 201 and the floating gate capacitive coupling 202. The potential of the floating gates of the unselected cells on WLn−1 and WLn+1 will be higher than other unselected cells due to this proximity. Additionally, word line-to-word line break down or leakage can be a problem, especially between the selected word line and the unselected, adjacent word lines.
If Vpass on WLn−1 and WLn−1 is reduced to prevent word line-to-word line breakdown issues, coupling disturb issues increase. If Vpass in adjacent word lines to Vpgm is decreased to prevent coupling disturb issues, the word line-to-word line breakdown issues increase.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to address the effects of program disturb in a memory device.